Research & Academic Projects

Dead-Field & Redundant Load Elimination Optimizer

Mentor: Prof. Manas Thakur | Course: Code Optimization for Object-Oriented Languages (CS6004) | Session: Spring 2026
Related to MS in Computer Science, CSE, IIT Bombay

Java Soot Framework Bytecode Transformation Static Program Analysis
  • Designed and implemented static analysis passes in the Soot framework to analyze object-oriented Java Bytecode.
  • Developed a Dead-Field Elimination pass that identifies unused or dead class attributes and removes their declarations/assignments.
  • Implemented a Redundant Load Elimination optimization to eliminate duplicate memory reads of fields, replacing them with local variable uses.
  • Built a suite of 10 evaluation testcases to evaluate correctness and runtime optimizations.
  • Measured runtime enhancements under interpretative execution (`-Xint` flag), recording significant percentage improvements in wall-clock execution time and call-site metrics.
GitHub Repository Read Report

Loop Iteration Count Predictor in ChampSim

Mentor: Prof. Biswabandan Panda | Research Group: CASPER Group (TRUST LAB) | Session: Spring 2026
Related to MS in Computer Science, CSE, IIT Bombay

C++ ChampSim Simulator Loop Predictor CPU Traces Computer Architecture
  • Designed and integrated a dynamic loop iteration count predictor into the ChampSim simulator.
  • Implemented tracing structures to identify loop boundaries and count dynamic iterations directly from compiled CPU instruction traces (e.g., SPEC, GAP, and Google workloads) without access to source code.
  • Analyzed backward branch behavior and PC history to track unique loops, profile dynamic iteration counts, and calculate detailed execution statistics.
  • Provided architectural insights by outputting loop frequency and termination boundaries, enabling potential optimizations in branch predictors and prefetchers.
GitHub Repository View Presentation

Implementation and Calculation of Cache Pollution

Mentor: Prof. Biswabandan Panda | Course: Advanced Computer Architecture | Session: Autumn 2025
Related to MS in Computer Science, CSE, IIT Bombay

C++ ChampSim Simulator Cache Hierarchy Systems Research
  • Designed and implemented custom instrumentation in the ChampSim simulator to quantify cache pollution at L1, L2, and Last-Level Cache (LLC).
  • Added an auxiliary tracking queue to temporarily store evicted cache lines, monitoring their potential future reuse patterns to track cache effectiveness.
  • Analyzed simulation benchmarks to determine the percentage of cache slots consumed by polluting lines.
GitHub Repository View Presentation

Key–Value Store with Multi-Threaded Load Generator

Course: Computer Systems & DBMS | Session: Autumn 2025

C++ MySQL Database REST API Multi-Threading LRU Cache
  • Designed and implemented a Key–Value Store in C++ supporting REST-based GET, POST, and DELETE operations.
  • Integrated an in-memory Least Recently Used (LRU) cache to optimize read performance and significantly reduce database access latency.
  • Connected the system to a MySQL database backend for persistent storage, structural schemas, and transactional durability.
  • Developed a multi-threaded load generator to simulate concurrent real-world workloads, including GET-heavy, write-heavy, mixed, and hot-key access patterns.
  • Measured, parsed, and analyzed system performance metrics such as throughput (requests/sec) and average response time under varying thread counts and cache configurations.
GitHub Repository View Performance Analysis